This invention relates to a fractional-N synthesiser and method of synchronisation in which the output is phase-synchronised to the input reference divided by the fractional modulus.
In a phase locked loop (PLL) the output signal is phase and frequency locked to an input reference signal. A PLL with a frequency divider inserted in the feedback loop can be used to make an Integer-N frequency synthesiser. In that case the signal at the phase detector negative input is phase and frequency locked to the reference. The output frequency and phase is N times the reference frequency and phase. Output frequencies can be synthesised in steps of the reference frequency by programming the value of N. There are exactly N periods of the output for every period of the reference and therefore one rising edge of the output in every N is in phase with each rising edge of the reference. For any given value of N the phase of the output relative to the reference is fixed and is the same each time the synthesiser is switched back to that frequency channel. In a fractional-N synthesiser, the divider in the feedback path has an integer and fractional part and the output frequency step resolution is a fraction of the reference frequency, as shown in equation 1:                               f                      O            ⁢                          xe2x80x83                        ⁢            U            ⁢                          xe2x80x83                        ⁢            T                          =                              (                          N              +                              F                M                                      )                    xc3x97                      f                          R              ⁢                              xe2x80x83                            ⁢              E              ⁢                              xe2x80x83                            ⁢              F                                                          (        1        )            
The fractional part is generated using a digital interpolator. This outputs a sequence of integer values with an average value given by F/M where F is the input fraction and M is the modulus. The modulus M can be programmable also or it may be fixed for a given implementation.
The interpolator could be for instance, a single accumulator with the overflow bit as output or it could be a higher order sigma-delta modulator. There are numerous prior art examples of both architectures.
Fractional-N synthesisers have a number of advantages which make them desirable. Their output steps are in fractions of the reference frequency. This allows the use of larger input reference frequencies which in turn allows N to be smaller. This is a major advantage because phase noise gain from input to output is a function of N2 or 20 Log N in dB""s so the noise can be much reduced by even a small reduction in N. Also the availability of a larger reference frequency allows a wider loop bandwidth which in turn allows a shorter settling time each time the synthesiser is switched from one frequency channel to another.
By rewriting equation (1) as follows:                               f                      O            ⁢                          xe2x80x83                        ⁢            U            ⁢                          xe2x80x83                        ⁢            T                          =                              (                                          M                ⁢                                  xe2x80x83                                ⁢                N                            +              F                        )                    xc3x97                                    f                              R                ⁢                                  xe2x80x83                                ⁢                E                ⁢                                  xe2x80x83                                ⁢                F                                      M                                              (        2        )            
it is clear that the output will only be in phase with one out of every M edges of the input reference. This highlights a major disadvantage of fractional-N synthesisers in that the output phase can have any one of M possible values with respect to the input reference phase, where M is the fractional modulus. Which one of the M edges of the reference this will be may be different each time the channel is synthesised depending on the particular state of the interpolator when the new N and F values, which specify the channel to be synthesised, are loaded. In some applications this doesn""t matter but when it is required that a particular output frequency signal has consistently the same phase relationship with a reference then this is a problem with a fractional-N synthesiser.
It is a primary object of this invention to provide a fractional-N synthesiser and method of synchronisation of the output phase with respect to a reference phase.
This invention results from the realization that a truly simple and effective fractional-N synthesiser with the output signal phase synchronised with the input reference signal can be achieved by generating a synchronisation pulse at integer multiples of periods of the input reference signal and gating one of those synchronisation pulses to re-initialise the interpolator in the fractional-N synthesiser to synchronise the phase of the output signal with the input reference signal.
This invention features a fractional-N synthesiser with synchronised output phase including a phased locked loop having an output signal whose frequency is a fractional multiple of the input reference signal. The phase locked loop includes a frequency divider. There is a synchronisation counter responsive to the input reference signal for generating synchronisation pulses at integer multiples of M periods of the input reference signal. An interpolator is responsive to an input fraction to provide to the frequency divider an output which has a fractional value equal to, on average, the input fraction. A gating circuit responsive to an enable signal passes a synchronisation pulse to re-initialise the interpolator to phase synchronise the output signal with the input reference signal.
In a preferred embodiment the frequency divider may include a dual modulus divider having moduli N and N+1. The frequency divider may alternatively include a programmable divider circuit and a summing circuit responsive to the interpolator output and an integer input. The gating circuit may pass the second or later synchronisation pulse after the occurrence of the enabled signal. The interpolator may be a modulo M interpolator.
This invention also features a method of phase synchronising the output signal with the input reference signal in a fractional-N synthesiser including generating a synchronisation pulse at integer multiples of periods of the input reference signal and gating a synchronisation pulse to re-initialise the interpolator in the fractional synthesiser to synchronise the phase of the output signal with the input reference signal.
In a preferred embodiment the synchronisation pulses may be generated at integer multiples of M periods where M is the modulus of the interpolator. The gating of the synchronisation pulse to re-initialise the interpolator may be enabled by a predetermined change in the frequency of the output signal.